Electrostatic discharge (ESD) is a sudden flow of electricity between objects caused by contact, electrical short, or dielectric breakdown. Integrated circuits are made from semiconductor materials such as silicon and insulating materials such as silicon dioxide. These materials may suffer permanent damage when subjected to high voltages resulted from an ESD event. Laterally diffused metal-oxide-semiconductor (LDMOS) transistors in an integrated circuit (IC) technology are widely used in power amplifiers for providing relatively high output power. Thus, an LDMOS transistor has a relatively high drain to source breakdown voltage, e.g., above 60 volts, compared to other devices such as gallium arsenide field effect transistors (GaAs FETs).
FIG. 1A illustrates a diagram of a cross section of a conventional LDMOS transistor 100. The LDMOS transistor 100 is built in a P-type substrate 110 and includes an N-type shallow drift region 108 in the substrate 110. The LDMOS transistor 100 further includes a body terminal 102, a source 104, and a drain 106. The body terminal 102 is a highly doped P-type region disposed in the substrate 110. The source 104 is a highly doped N-type region disposed in the substrate 110. The drain 106 is a highly doped N-type region disposed in the shallow drift region 108. A gate 124 is separated from the transistor body by a gate oxide 120 and a thick oxide 122.
A snap-back effect indicating a positive feedback condition may occur when an ESD pulse (e.g., up to 1,000 volts voltage within 1 micro second) is applied to the drain 106, e.g., due to unexpected contact, electrical short, or dielectric breakdown. More specifically, if an ESD pulse is applied to the drain 106, holes in a first region of the substrate 110 is depleted (e.g., the holes flow away through the source 104). Consequently, negative ionic charges emerge in the first region near a frontier 116 between the substrate 110 and the shallow drift region 108 (the first region is represented by “−” as shown in FIG. 1A). Moreover, electrons in a second region of the shallow drift region 108 are depleted (e.g., the electrons flow away through the drain 106). As a result, positive ionic charges emerge in the second region near the frontier 116 (the second region is represented by “+” as shown in FIG. 1A). The first region in the substrate 110 and the second region in the shallow drift region 108 constitute a depletion region in the LDMOS transistor 100. The negative ions and the positive ions establish high electric fields in the depletion region.
FIG. 1B illustrates another diagram of a cross section 120 of the LDMOS transistor 100. The depletion region in the transistor 100 includes multiple PN junctions at the frontier 116. For example, the regions A1 and A2 constitute a PN junction A1-A2; the regions B1 and B2 constitute a PN junction B1-B2; and the regions C1 and C2 constitute a PN junction C1-C2. Once the electric field of a PN junction reaches a threshold, e.g., when the voltage of the PN junction reaches a breakdown voltage, the PN junction is broken down and an avalanche multiplication effect is triggered to generate a large amount of electron-hole pairs. Therefore, the substrate current flowing from the drain 106 to the source 104 abruptly increases, which forward biases a PN junction between the source 104 and the substrate 110. Through the forward-biased PN junction, the source 108 continually provides electrons to the high electrical field region, further increasing the substrate current. Therefore, a positive feedback status (the snap-back effect) is established, during which the substrate current can continue to increase. Furthermore, as a great amount of holes emerge in the substrate 110, the voltage of the substrate 110 is increased, and thus the inverse voltage across the PN junction decreases.
The dopant density in the substrate 110 or the shallow drift region 108 is not uniformly distributed due to fabrication processes. PN junctions A1-A2, B1-B2, and C1-C2 are at different depths at the frontier 116. By way of example, in the substrate 116, the dopant density of the P-type region A1 can be greater than that of the region B1, which can be greater than that of the region C1. Similarly, in the shallow drift region 108, the dopant density of the N-type region A2 can be greater than that of the region B2, which can be greater than that of the region C2.
FIG. 1C shows a diagram 140 illustrating electric fields in the LDMOS transistor 100. An electric field at a particular position in the LDMOS transistor 100 is determined by the dopant density at the position and a distance Xd between the position and the frontier 116. As shown in FIG. 1C, the lines 142, 144, and 146 respectively show the electric fields of regions having dopant densities D142, D144, and D146, where D142 is greater than D144 which is greater than D146. The electric field decreases as the distance Xd increases. XA2, XB2, and XC2 represent distances between the boundaries of the depletion regions and the frontier 116. At the distances XA2, XB2, and XC2, the electric field decreases to zero. As shown in FIG. 1A (by way of example), an electric field at the point P1 is greater than an electric field at the point P2, because P1 is closer to the frontier 116 (assuming the dopant densities at the points P1 and P2 are the same). Moreover, if different positions have the same distance Xd and different dopant densities, then the position having a lower dopant density can have a higher electric field. For example, in FIG. 1C, at the same distance Xd1, the electric filed E146 is greater than E144, which is greater than E142.
The breakdown voltage of a PN junction can be calculated according to an integral of the electric field with respect to the distance Xd. In other words, an area enclosed by a corresponding line 142, 144 or 146, axis Xd and axis E represents a breakdown voltage of a corresponding PN junction. For example, an area formed by the axis Xd, the axis E, and the line 142 represents a breakdown voltage V142 for the PN junction having the dopant density D142. An area formed by the axis Xd, the axis E, and the line 144 represents a breakdown voltage V144 for the PN junction having the dopant density D144. An area formed by the axis Xd, the axis E, and the line 146 represents a breakdown voltage V146 for the PN junction having the dopant density D146. In the example of FIG. 1C, the voltage V142 is less than the voltage V144, which is less than the voltage V146. Therefore, as shown in FIG. 1B, a breakdown voltage VA1-A2 at the PN junction A1-A2 is less than a breakdown voltage VB1-B2 at the PN junction B1-B2, which is less than a breakdown voltage VC1-C2 at the PN junction C1-C2.
FIG. 1D illustrates a diagram 160 of currents through PN junctions on the frontier 116 versus inverse voltages across the PN junctions. The curves 162, 164 and 166 represent the currents versus inverse voltages across the PN junctions A1-A2, B1-B2 and C1-C2, respectively. Taking the curve 162 for example, when an inverse voltage of the PN junction A1-A2 increases from zero volts to the breakdown voltage VA1-A2, the current of the PN junction A1-A2 slightly increases from zero amperes. Once the inverse voltage reaches the breakdown voltage VA1-A2, the PN junction A1-A2 is broken down. Then, the current of the PN junction A1-A2 rapidly increases because of the snap-back effect, and the inverse voltage across the PN junction A1-A2 decreases. The PN junctions B1-B2 and C1-C2 operate similarly as the PN junction A1-A2 with respect to their own breakdown voltages VB1-B2 and VC1-C2.
However, the ESD performance of the LDMOS transistor 100 may be problematic. As discussed in relation to FIG. 1C, different PN junctions have different breakdown voltages. Thus, when an ESD pulse is applied to the drain 106, one PN junction on the frontier 116 is broken down while the others are not. For example, when the voltage of the drain 106 increases to the voltage VA1-A2, e.g., due to an ESD pulse, only the PN junction A1-A2 is broken down to generate an abruptly increased current. At that moment, the PN junctions B1-B2 and C1-C2 experience relatively little current. Since large portions of energy are released through the relatively small regions A1 and A2, the abruptly increased current of the PN junction A1-A2 may damage the regions A1 and A2. As such, the LDMOS transistor 100 may be damaged, and the lifetime of the LDMOS transistor 100 may be shortened.